Circuit and method for impedance matching

ABSTRACT

An impedance matching circuit ( 10 ) matches the impedance of a load ( 19 ) coupled to an RF amplifier ( 12 ) to that of the RF amplifier ( 12 ). The impedance matching circuit ( 10 ) samples a transmitted signal from the RF amplifier ( 12 ) and a reflected signal from the load ( 19 ). The amplitude and the phase of the sampled reflected signal are compared with those of the sampled transmitted signal to calculate the impedance mismatch. A control logic circuit ( 80 ) adjusts the capacitance and inductance values of variable capacitance ( 23, 27 ) and inductance ( 35 ) elements in the impedance matching circuit ( 10 ), thereby matching the impedance of the load ( 19 ) to that of the RF amplifier ( 12 ).

BACKGROUND OF THE INVENTION

[0001] The present invention relates, in general, to semiconductor circuits and, more particularly, to Radio Frequency (RF) circuits.

[0002] The performance of an RF power amplifier depends on the impedance of a load coupled to the output of the RF power amplifier. An RF power amplifier is generally designed to perform optimally when the load impedance has a predetermined value such as, for example, 50 ohms (Ω). When the load impedance differs from the predetermined value, the performance, such as output power, efficiency, linearity, etc., of the power amplifier is degraded.

[0003] In communication applications, an RF power amplifier is typically used to amplify an RF signal before the RF signal is transmitted through an antenna. The impedance of the antenna depends on the environment in which the antenna operates. In order to maintain an optimum performance of the power amplifier in various environments, an isolator is coupled between the power amplifier and the antenna. The isolator, which is also referred to as a circulator, has a first terminal coupled to the output of the power amplifier, a second terminal coupled to the antenna, and a third terminal coupled to ground via a device having a fixed impedance, e.g., 50 Ω. The output signal of the power amplifier is transmitted to the antenna through the first and second terminals of the isolator. The signal reflected back from the antenna due to an impedance mismatch is transmitted to ground via the third terminal of the isolator and the fixed impedance device. Thus, the impedance mismatch of the antenna does not affect the performance of the power amplifier. However, an isolator is big, expensive, and power inefficient. It is not suitable for use in low cost, low power, portable communication systems.

[0004] Accordingly, it would be advantageous to have a circuit and a method for maintaining the optimum performance of a power amplifier under various operating conditions. It is desirable for circuit to be simple and inexpensive. It is also desirable for the circuit to be small. It would be of further advantage for the method to be power efficient and suitable for use in low power applications.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005]FIG. 1 is a schematic diagram of an impedance matching circuit in accordance with a first embodiment of the present invention; and

[0006]FIG. 2 is a schematic diagram of an impedance matching circuit in accordance with a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0007] Generally, the present invention provides a circuit and a method for impedance matching between two circuit elements such as, for example, a power amplifier and an antenna. In accordance with the present invention, an impedance matching circuit is coupled between the two circuit elements. The impedance matching circuit samples a signal transmitted from the first circuit element to the second circuit element and a signal that may be reflected back from the second circuit element when there is an impedance mismatch between the two circuit elements. The amplitudes and the phases of the two sampled signals are compared with each other to calculate the impedance mismatch. A control logic circuit adjusts the capacitance and inductance values of variable capacitance and inductance elements in the impedance matching circuit, thereby matching the impedance of the second circuit element to that of the first circuit element and maintaining an optimum operating condition for the first circuit element.

[0008]FIG. 1 is a schematic diagram of an impedance matching circuit 10 in accordance with a first embodiment of the present invention. Impedance matching circuit 10, which is also referred to as an impedance matching network, has an input terminal 11 coupled to a driver 12, e.g., a power amplifier, and an output terminal 18 coupled to a load 19, e.g., an antenna. By way of example, driver 12 is designed to perform optimally when its load is a resistive load having an input impedance of approximately 50 ohms (Ω). In operation, impedance matching circuit 10 maintains an input impedance of approximately 50 Ω at terminal 11, thereby maintaining an optimal operating condition for driver 12. Impedance matching circuit 10 can be implemented as an integrated circuit, a discrete circuit, or a hybrid circuit.

[0009] Impedance matching circuit 10 includes an interface circuit 20 comprised of capacitance elements 23 and 27, an inductance element 35, and capacitors 42, 44, 46, and 48. Capacitor 42 provides direct current (DC) signal isolation between terminal 11 and capacitance element 23. Capacitor 44 provides DC signal isolation between capacitance element 23 and inductance element 35. Capacitor 46 provides DC signal isolation between inductance element 35 and capacitance element 27. Capacitor 48 provides DC signal isolation between capacitance element 27 and terminal 18. Thus, capacitors 42, 44, 46, and 48 are also referred to as DC signal blocking capacitors. If impedance matching circuit 10 is implemented as a hybrid circuit, the capacitance values of capacitors 42, 44, 46, and 48 are preferably such that they are self-resonant over the frequency range in which impedance matching circuit 10 operates. By way of example, the capacitance values of capacitors 42, 44, 46, and 48 are between approximately 10 pico-Farads (pF) and approximately 50 pF. It should be noted that it is not necessary for capacitors 42, 44, 46, and 48 to have the same capacitance.

[0010] Capacitance element 23 includes a voltage controlled variable capacitor 22 and a resistor 24. A first electrode of capacitor 22 and a first electrode of resistor 24 are connected together to form a first terminal of capacitance element 23, which is connected to one electrode of capacitor 42. The other electrode of capacitor 42 forms an input of interface circuit 20 and is connected to terminal 11 of impedance matching circuit 10. A second electrode of capacitor 22 forms a second terminal of capacitance element 23 and is connected for receiving a reference voltage at a voltage supply conductor 30. By way of example, conductor 30 is at ground voltage level. A second electrode of resistor 24 forms a control terminal 25 of capacitance element 23. The capacitance of capacitor 22 can be adjusted by a voltage signal applied to control terminal 25. Therefore, capacitance element 23 is also referred to as a variable capacitance element or an adjustable capacitance element. Capacitor 22 is referred to as a shunt capacitor. By way of example, the capacitance of capacitor 22 varies over a range from approximately 1 pF to approximately 10 pF, and the resistance of resistor 24 is between approximately 5 kiloohms (kΩ) and approximately 20 kΩ.

[0011] Capacitance element 27 includes a voltage controlled variable capacitor 26 and a resistor 28. A first electrode of capacitor 26 and a first electrode of resistor 28 are connected together to form a first terminal of capacitance element 27, which is connected to one electrode of capacitor 48. The other electrode of capacitor 48 forms an output of interface circuit 20 and is coupled to terminal 18 of impedance matching circuit 10. A second electrode of capacitor 26 forms a second terminal of capacitance element 27 and is connected for receiving the reference voltage at voltage supply conductor 30. A second electrode of resistor 28 forms a control terminal 29 of capacitance element 27. The capacitance of capacitor 26 can be adjusted by a voltage signal applied to control terminal 29. Therefore, capacitance element 27 is also referred to as a variable capacitance element or an adjustable capacitance element. Capacitor 26 is referred to as a shunt capacitor. By way of example, the capacitance of capacitor 26 varies over a range from approximately 1 pF to approximately 10 pF, and the resistance of resistor 28 is between approximately 5 kΩ and approximately 20 kΩ.

[0012] Inductance element 35 includes an inductor 32, a voltage controlled variable capacitor 34, and resistors 36 and 38. A first electrode of inductor 32 forms a first terminal of inductance element 35 and is coupled to the first terminal of capacitance element 23 via capacitor 44. A second electrode of inductor 32 is connected to a first electrode of capacitor 34 and to a first electrode of resistor 36. A second electrode of capacitor 34 and a first electrode of resistor 38 are connected together to form a second terminal of inductance element 35, which is coupled to the first terminal of capacitance element 27 via capacitor 46. A second electrode of resistor 36 is connected for receiving the reference voltage at voltage supply conductor 30. A second electrode of resistor 38 forms a control terminal 39 of inductance element 35. Preferably, the impedance of inductor 32 and the impedance of capacitor 34 over the frequency range in which impedance matching circuit 10 operates are such that inductance element 35 is effectively an inductive element. The inductance of inductance element 35 is determined by the inductance of inductor 32 and the capacitance of capacitor 34. Because the capacitance of capacitor 34 can be adjusted by a voltage signal applied to control terminal 39, the inductance of inductance element 35 is also adjustable. Therefore, inductance element 35 is referred to as a variable inductance element or an adjustable inductance element. Inductor 32 and capacitor 34 are referred to as a series inductor and a series capacitor, respectively. By way of example, the inductance of the inductor 32 is between approximately 5 nano-henries (nH) and approximately 40 nH, the capacitance of capacitor 34 varies over a range from approximately 1 pF to approximately 10 pF, and the resistance values of resistors 36 and 38 are between approximately 5 kΩ and approximately 20 kΩ.

[0013] The capacitance values of capacitance elements 23 and 27, and the inductance value of inductance element 35 are adjustable via voltage signals at control terminals 25, 29, and 39, respectively. Interface circuit 20 maintains a predetermined impedance, e.g., approximately 50 Ω, at terminal 11. Driver 12 is designed to perform optimally at the predetermined impedance value. When the input impedance of load 19 differs from the predetermined impedance, there is an impedance mismatch between load 19 and driver 12. Impedance mismatch is typically calculated using a Smith Chart, which is well known to those skilled in the art. It should be understood that driver 12 can also be designed to perform optimally at other impedance values. Therefore, impedance matching circuit 10 is not limited to matching the input impedance of load 19 to 50 Ω. For example, impedance matching circuit 10 can be designed to match the input impedance of load 19 to other predetermined impedance values such as, for example, 25 Ω, 75 Ω, 100 Ω, etc.

[0014] In one embodiment, the signal transmitted from driver 12 to load 19 is a Radio Frequency (RF) signal having a frequency of approximately 900 mega-Hertz and inductor 32 has an inductance of approximately 18 nH. Interface circuit 20 is capable of maintaining an input impedance of approximately 50 Ω at terminal 11 when the mismatch between the input impedance of load 19 and the predetermined impedance value is within a predetermined range. For example, interface circuit 20 is capable of maintaining the predetermined impedance at terminal 11 when the magnitude of the impedance mismatch between the input impedance of load 19 and the predetermined impedance is no greater than approximately three times the magnitude of the predetermined impedance, i.e., the mismatch is no greater than approximately 3:1. This is true regardless of whether load 19 is a resistive load, a capacitive load, or an inductive load.

[0015] In another embodiment, the signal transmitted from driver 12 to load 19 is an RF signal having a frequency of approximately 1.9 giga-Hertz and inductor 32 has an inductance of approximately 8.2 nH. Interface circuit 20 is able to maintaining an input impedance of approximately 50 Ω at terminal 11 when the mismatch between the input impedance of load 19 and the predetermined impedance value is within a range no greater than approximately 3:1. This is also true regardless of whether load 19 is a resistive load, a capacitive load, or an inductive load.

[0016] However, the environment in which load 19 operates may cause the input impedance of load 19 to vary only over a limited range. For example, load 19 may be either a resistive load or a capacitive load, but not an inductive load. Thus, it is not always necessary for interface circuit 20 to be able to maintain the predetermined impedance value at terminal 11 regardless of whether load 19 is a resistive load, a capacitive load, or an inductive load. In other words, it is not always necessary for interface circuit 20 to have the full range impedance matching capability as described hereinbefore. A limited impedance matching capability is sometimes sufficient to maintain an optimum operating condition for driver 12. In this case, one of the two shunt capacitors 22 and 26 can be replaced by a fixed capacitor. Therefore, either capacitance element 23 or capacitance element 27 can be a capacitance element with a fixed capacitance value.

[0017] Impedance matching circuit 10 also includes a Voltage Standing Wave Ratio (VSWR) detection element 50 comprised of a bidirectional coupler 55, a phase comparator 57, and a magnitude comparator 60. A terminal 51 of coupler 55 serves as a first terminal of VSWR detection element 50 and is connected to the output of interface circuit 20. A terminal 52 of coupler 55 serves as a second terminal of VSWR detection element 50 and is connected to terminal 18 of impedance matching circuit 10. Coupler 55 also has sampling ports 53 and 54. In operation, a sampled signal is generated at sampling port 53 in accordance with a signal transmitted from driver 12 to load 19 via coupler 55. Likewise, a sampled signal is generated at sampling port 54 in accordance with a signal reflected back from load 19. Bidirectional couplers are well known to those skilled in the art.

[0018] Phase comparator 57 includes a mixer 56 and a low pass filter 58. A first signal port such as, for example, an RF port of mixer 56 serves as a first input of phase comparator 57 and is connected to sampling port 53 of coupler 55. A second signal port such as, for example, a Local Oscillator (LO) port of mixer 56 serves as a second input of phase comparator 57 and is connected to sampling port 54 of coupler 55. An output port such as, for example, an Intermediate Frequency (IF) port of mixer 56 is connected to an input of low pass filter 58. An output of low pass filter 58 serves as an output of phase comparator 57 and is connected to a VSWR phase output 59 of VSWR detection element 50.

[0019] Magnitude comparator 60 includes peak detectors 61 and 62, and a differential amplifier 74. Peak detector 61 rectifies a sampled signal from sampling port 53 and generates a low frequency signal which is substantially proportional to the amplitude of the signal at sampling port 53. Likewise, peak detector 62 rectifies a sampled signal from sampling port 54 and generates a low frequency signal which is substantially proportional to the amplitude of the signal at sampling port 54. Peak detectors 61 and 62 are also referred to as rectifiers. Differential amplifier 74 compares the two low frequency signals transmitted from rectifiers 61 and 62 and generates an output signal that is substantially proportional to a ratio of the amplitude of the sampled signal at sampling port 53 to that of the sampled signal at sampling port 54.

[0020] Rectifier 61 is comprised of a diode 63, a resistor 65, and a capacitor 67. An anode of diode 63 serves as a first input of magnitude comparator 60 and is connected to sampling port 53 of coupler 55. A cathode of diode 63, a first electrode of resistor 65, and a first electrode of capacitor 67 are connected together to form an output of rectifier 61, which is connected to a first input of differential amplifier 74. A second electrode of resistor 65 and a second electrode of capacitor 67 are connected for receiving the reference voltage at voltage supply conductor 30. Resistor 65 and capacitor 67 form a low pass filter 71 in rectifier 61. Likewise, rectifier 62 is comprised of a diode 64, a resistor 66, and a capacitor 68. An anode of diode 64 serves as a second input of magnitude comparator 60 and is connected to sampling port 54 of coupler 55. A cathode of diode 64, a first electrode of resistor 66, and a first electrode of capacitor 68 are connected together to form an output of rectifier 62, which is connected to a second input of differential amplifier 74. A second electrode of resistor 66 and a second electrode of capacitor 68 are connected for receiving the reference voltage at voltage supply conductor 30. Resistor 66 and capacitor 68 form a low pass filter 72 in rectifier 62. An output of differential amplifier 74 is connected to a VSWR magnitude output 79 of VSWR detection element 50.

[0021] It should be understood that the structure of VSWR detection element 50 is not limited to that shown in FIG. 1. Any circuit that is capable of comparing the phases and magnitudes of two signals of substantially the same frequency can replace VSWR detection element 50 in impedance matching circuit 10.

[0022] Impedance matching circuit 10 further includes a control logic circuit 80. A first input of control logic circuit 80 is connected to VSWR phase output 59 of VSWR detection element 50. A second input of control logic circuit 80 is connected to VSWR magnitude output 79 of VSWR detection element 50. Control logic circuit 80 also has three outputs which are connected to corresponding control terminals 25, 29, and 39 of interface circuit 20.

[0023] In operation, a signal is transmitted from driver 12 to load 19 via impedance matching circuit 10. In response to the transmitted signal, a signal will be reflected back to impedance matching circuit 10 if the input impedance of load 19 has a mismatch from the predetermined impedance value, e.g., approximately 50 Ω. The reflected signal is transmitted to terminal 52 of coupler 55. Coupler 55 samples the transmitted signal at terminal 51 and the reflected signal at terminal 52, thereby generating a sampled transmitted signal and a sampled reflected signal at sampling ports 53 and 54, respectively. Preferably, the amplitudes of the sampled transmitted signal at sampling port 53 and the sampled reflected signal at sampling port 54 are proportional to the amplitudes of the transmitted signal at terminal 51 and the reflected signal at terminal 52, respectively, and the two coefficients of proportionality are substantially equal to each other.

[0024] Mixer 56 in phase comparator 57 mixes the sampled transmitted signal and the sampled reflected signal to generate a multiplied signal at its output port. Because the transmitted signal and the reflected signal have the same frequency as each other, a low frequency component of the multiplied signal is substantially proportional to the phase difference between the two signals. This low frequency component of the multiplied signal is also referred to as a phase signal of VSWR detection element 50. The phase signal is transmitted through low pass filter 58 to VSWR phase output 59.

[0025] Rectifiers 61 and 62 rectify the sampled transmitted signal from sampling port 53 and the sampled reflected signal from sampling port 54, respectively, of coupler 55. Differential amplifier 74 compares the two rectified signals and generates an output signal that is substantially proportional to a ratio of the amplitude of the sampled transmitted signal to the amplitude of the sampled reflected signal. The output signal of differential amplifier 74 is also referred to as a magnitude signal of VSWR detection element 50. The magnitude signal is transmitted to VSWR magnitude output 79.

[0026] Control logic circuit 80 receives two control signals from VSWR detection element 50. The first control signal is the phase signal at VSWR phase output 59, and the second control signal is the magnitude signal at VSWR magnitude output 79. Based on these control signals, control logic circuit 80 generates voltage signals for adjusting capacitors 22, 26, and 34 in interface circuit 20. In one example, a memory unit (not shown), e.g., a Static Random Access Memory (SRAM) unit, in control logic circuit 80 stores a look-up table of the desired voltage values for the voltage signals corresponding to various values of the phase and magnitude signals. In another example, an algorithm is used to calculate the desired voltage values for the voltage signals corresponding to various values of the phase and magnitude signals.

[0027] Interface circuit 20 receives the voltage signals of control logic circuit 80 via control terminals 25, 29, and 39 and uses the voltage signals to adjust the capacitance values of corresponding capacitors 22, 26, and 34. The voltage signal at control terminal 25 provides a voltage bias to capacitor 22 via resistor 24 and adjusts the capacitance value of capacitance element 23. The voltage signal at control terminal 29 provides a voltage bias to capacitor 26 via resistor 28 and adjusts the capacitance value of capacitance element 27. The voltage signal at control terminal 39 provides a voltage bias to capacitor 34 via resistors 36 and 38 and adjusts the capacitance of capacitor 34 and the inductance value of inductance element 35. Capacitance elements 23 and 27, and inductance element 35 cooperate to maintain an input impedance of approximately 50 Ω at terminal 11, thereby optimizing the performance of driver 12.

[0028]FIG. 2 is a schematic diagram of an impedance matching circuit 110 in accordance with a second embodiment of the present invention. Impedance matching circuit 110, which is also referred to as an impedance matching network, has a terminal 111 coupled to a first circuit element, e.g., a power amplifier 112, and a terminal 118 coupled to a second circuit element, e.g., a load 119 of power amplifier 112. Impedance matching circuit 110 can be implemented as an integrated circuit, a discrete circuit, or a hybrid circuit.

[0029] Power amplifier 112 typically includes several amplification stages. An amplification stage 113 is shown in FIG. 2 as the last amplification stage in power amplifier 112. An inductor 114 and a capacitor 116 form an impedance matching element 115 in power amplifier 112. Inductor 114 has one electrode connected to an output of amplification stage 113. The other electrode of inductor 114 is connected to an electrode of capacitor 116 to form a node 117, which is connected to terminal 111. The other electrode of capacitor 116 is connected to a voltage supply conductor 130. By way of example, voltage supply conductor 130 is at ground voltage level.

[0030] Impedance matching circuit 110 includes an interface circuit 120 that matches the input impedance at terminal 111 to the output impedance of power amplifier 112 at the node 117. Interface circuit 120 is comprised of a capacitance element 127, an inductance element 135, and capacitors 144, 146, and 148. Capacitor 144 provides DC signal isolation between terminal 111 and inductance element 135. Capacitor 146 provides DC signal isolation between inductance element 135 and capacitance element 127. Capacitor 148 provides DC signal isolation between capacitance element 127 and terminal 118. Thus, capacitors 144, 146, and 148 are also referred to as DC signal blocking capacitors. By way of example, the capacitance values of capacitors 144, 146, and 148 are between approximately 10 pF and approximately 50 pF. If impedance matching circuit 110 is implemented as a hybrid circuit, the capacitance values of capacitors 144, 146, and 148 are preferably such that they are self-resonant over the frequency range in which impedance matching circuit 110 operates. It should be noted that it is not necessary for capacitors 144, 146, and 148 to have the same capacitance.

[0031] Inductance element 135 includes an inductor 132, a voltage controlled variable capacitor 134, and resistors 136 and 138. A first electrode of inductor 132 forms a first terminal of inductance element 135 and is coupled to terminal 111 via capacitor 144. A second electrode of inductor 132 is connected to a first electrode of capacitor 134 and to a first electrode of resistor 136. A second electrode of capacitor 134 and a first electrode of resistor 138 are connected together to form a second terminal of inductance element 135. A second electrode of resistor 136 is connected for receiving a reference voltage at voltage supply conductor 130. A second electrode of resistor 138 forms a control terminal 139 of inductance element 135. Preferably, the impedance of inductor 132 and the impedance of capacitor 134 over the frequency range in which impedance matching circuit 110 operates are such that inductance element 135 is effectively an inductive element whose inductance is determined by the inductance of inductor 132 and the capacitance of capacitor 134. Because the capacitance of capacitor 134 can be adjusted by a voltage signal applied to control terminal 139, the inductance of inductance element 135 is also adjustable. Therefore, inductance element 135 is referred to as a variable inductance element or an adjustable inductance element. By way of example, the inductance of inductor 132 is between approximately 5 nH and approximately 40 nH, the capacitance of capacitor 134 varies over a range from approximately 1 pF to approximately 10 pF, and the resistance values of resistors 136 and 138 are between approximately 5 kΩ and approximately 20 kΩ.

[0032] Capacitance element 127 includes a voltage controlled variable capacitor 126 and a resistor 128. A first electrode of capacitor 126 and a first electrode of resistor 128 are connected together to form a first terminal of capacitance element 127, which is coupled to the second terminal of inductance element 135 via capacitor 146 and connected to one electrode of capacitor 148. The other electrode of capacitor 148 forms an output of interface circuit 120 and is coupled to terminal 118 of impedance matching circuit 110. A second electrode of capacitor 126 forms a second terminal of capacitance element 127 and is connected for receiving the reference voltage at voltage supply conductor 130. A second electrode of resistor 128 forms a control terminal 129 of capacitance element 127. The capacitance of capacitor 126 can be adjusted by a voltage signal applied to control terminal 129. Therefore, capacitance element 127 is also referred to as a variable capacitance element or an adjustable capacitance element. By way of example, the capacitance of capacitor 126 varies over a range from approximately 1 pF to approximately 10 pF, and the resistance of resistor 128 is between approximately 5 kΩ and approximately 20 kΩ.

[0033] Impedance matching circuit 110 also includes a phase and magnitude detection element 150, which has a first terminal connected the output of interface circuit 120 and a second terminal connected to terminal 118 of impedance matching circuit 110. Phase and magnitude detection element 150 also has a phase output 159 and a magnitude output 179. In a preferred embodiment, phase and magnitude detection element 150 is functionally identical to VSWR detection element 50 of impedance matching circuit 10 shown in FIG. 1.

[0034] Impedance matching circuit 110 further includes a control logic circuit 180. A first input of control logic circuit 180 is connected to phase output 159 of phase and magnitude detection element 150. A second input of control logic circuit 180 is connected to magnitude output 179 of phase and magnitude detection element 150. Control logic circuit 180 also has two outputs which are connected to corresponding control terminals 129 and 139 of interface circuit 120.

[0035] In operation, a signal is transmitted from power amplifier 112 to load 119 via impedance matching circuit 110. If there is an impedance mismatch between load 119 and power amplifier 112, a signal is reflected back to impedance matching circuit 110. Phase and magnitude detection element 150 compares the phase and magnitude of the reflected signal with those of the transmitted signal and generates two control signals. The first control signal is a phase signal at phase output 159, and the second control signal is a magnitude signal at magnitude output 179.

[0036] Control logic circuit 180 receives the two control signals from phase and magnitude detection element 150. Based on these control signals, control logic circuit 180 generates voltage signals for adjusting capacitors 126 and 134 in interface circuit 120. In one example, a memory unit (not shown), e.g., an SRAM unit, in control logic circuit 180 stores a look-up table of the desired voltage values for the voltage signals corresponding to various values of the phase and magnitude signals. In another example, an algorithm is used to calculate the desired voltage values for the voltage signals corresponding to various values of the phase and magnitude signals.

[0037] Interface circuit 120 receives the voltage signals of control logic circuit 180 via control terminals 129 and 139. The voltage signal at control terminal 129 provides a voltage bias to capacitor 126 via resistor 128 and adjusts the capacitance value of capacitance element 127. The voltage signal at control terminal 139 provides a voltage bias to capacitor 134 via resistors 136 and 138 and adjusts the capacitance of capacitor 134 and the inductance value of inductance element 135. Capacitance element 127 and inductance element 135 cooperate to match the input impedance at terminal 111 to the output impedance of power amplifier 112, thereby by optimizing the performance of power amplifier 112.

[0038] Compared with impedance matching circuit 10 shown in FIG. 1, impedance matching circuit 110 has fewer elements, and is simpler and more cost efficient. On the other hand, impedance matching circuit 10 shown in FIG. 1 matches the input impedance of a load to a predetermined impedance value, e.g., 50 Ω, which is a standardized impedance in RF circuits. Therefore, impedance matching circuit 10 can work with any circuit element having a predetermined impedance.

[0039] By now it should be appreciated that a circuit and a method for impedance matching between two circuit elements have been provided. The impedance matching circuit samples a signal transmitted from the first circuit element to the second circuit element and a second signal that may be reflected back from the second circuit element when there is an impedance mismatch between the two circuit elements. The amplitude and the phase of the second sampled signal are compared with those of the first sampled signal to calculate the impedance mismatch. A control logic circuit adjusts the capacitance and inductance values of variable capacitance and inductance elements in the impedance matching circuit, thereby matching the input impedance of the second circuit element to the output impedance of the first circuit element and maintaining an optimum operating condition for the first circuit element. Compared with prior art isolators, the impedance matching circuit of the present invention is small, simple, and inexpensive. In addition, the circuit and the method of the present invention are power efficient and suitable for use in low power applications. 

16. A method for impedance matching, comprising the steps of: sampling a first signal transmitted from a first circuit element to a second circuit element; sampling a second signal reflected from the second circuit element in response to the first signal; generating a first control signal in accordance with an amplitude of the first signal and an amplitude of the second signal; generating a second control signal in accordance with a phase of the first signal and a phase of the second signal; and adjusting an interface network in accordance with the first control signal and the second control signal.
 17. The method as claimed in claim 16, wherein: the step of sampling a first signal includes generating a first sampled signal; the step of sampling a second signal includes generating a second sampled signal; the step of generating a first control signal includes generating the first control signal based on a ratio of an amplitude of the first sampled signal to an amplitude of the second sampled signal; and the step of generating a second control signal includes generating the second control signal based on a difference between a phase of the first sampled signal and a phase of the second sampled signal.
 18. The method as claimed in claim 16, wherein the step of adjusting the interface network includes matching an input impedance of the second circuit element to an output impedance of the first circuit element.
 19. The method as claimed in claim 16, wherein the step of adjusting the interface network includes the steps of: generating a plurality of voltage signals in accordance with the first control signal and the second control signal; and applying the plurality of voltage signals to the interface network.
 20. The method as claimed in claim 19, wherein the step of adjusting the interface network further includes the steps of: using a first voltage signal of the plurality of voltage signals to adjust a capacitance of a first shunt capacitor in the interface network, the first shunt capacitor being coupled between the first circuit element and a reference voltage; using a second voltage signal of the plurality of voltage signals to adjust a capacitance of a second shunt capacitor in the interface network, the second shunt capacitor being coupled between the second circuit element and the reference voltage; and using a third voltage signal of the plurality of voltage signals to adjust a capacitance of a series capacitor in the interface network, the series capacitor being coupled in series with an inductor between the first circuit element and the second circuit element. 